The present invention generally relates to a semiconductor integrated circuit device having multilayer power supply lines, and in particular to a semiconductor integrated circuit device having multilayer power supply lines arranged at three or more layer levels
A power supply line formed on a semiconductor chip is mainly composed of a high-voltage power supply line and a low-voltage power supply line which are arranged in a peripheral area of the semiconductor chip. A plurality of branch power supply lines extend from each of the high-voltage power supply line and the low-voltage power supply line, and pass over cells (basic cells provided in a gate array device, or a circuit block constructing an inverter, an NAND gate, an NOR gate or the like in a standard cell) arranged in the chip. The branches of the high-voltage power supply line and the low-voltage power supply line are connected to predetermined positions on the cells.
It is well known that an integrated circuit becomes more complex and a supply current fed to the integrated circuit becomes greater as the integration density of the semiconductor integrated circuit device increases. On the other hand, an increased integration density necessarily requires a decrease in the size of the integrated circuit formed in the chip. From these viewpoints, recently, there has been considerable activity in the development of a multilayer power supply line. At current, a semiconductor integrated circuit device having power supply lines arranged at three layer levels has been presented in practical use. In the conventional three-level (three-layer) power supply lines, a plurality of lower-level (first level) power supply lines and a plurality of upper-level (third level) power supply lines extend in the same direction. It is to be noted that "a level" is a term with respect to a layer. One lower-level power supply line and one upper-level power supply lines are set at the same potential, and are arranged so as to overlap each other in the elevational direction of the device. A plurality of an intermediate-level (second level) power supply lines positioned at an intermediate layer level are separated from each other with a predetermined pitch and are arranged in a direction perpendicular to the upper and lower power supply lines. Elevationally adjacent lines may be connected to each other by a contact. One upper-level power supply line may be connected to one lower-level power supply line by two different contacts, one of which is used for establishing a connection between the lower-level and intermediate-level power supply lines, and the other of which is used for establishing a connection between the intermediate-level and the upper-level power supply lines. This configuration is disclosed in U.S. Pat. No. 4,661,815.
However, the conventional multilayer power supply line structure has the following disadvantages. First, a connection path between the lower-level and the upper-level power supply lines is very long due to the layer structure that the overlapping lower-level and upper-level power supply lines are set at the same, potential. Therefore, the connecting path has a large wiring resistance and therefore a current passing therethrough is considerably consumed. Secondly, as described in detail later, a large current capacity is required for the lower-level power supply lines, and therefore the lower-level power supply lines must be made relatively wide. In this case, there is less worth using the upper-level power supply line. Thirdly, the distance between power supply lines of different potentials such as a V.sub.DD line and a V.sub.SS line is great, and a coupling capacitance therebetween is therefore small. For this reason, the stabilization in the power supply voltages resulting from the capacitive coupling is less expected.